Approaches to Test Generation

A variety of methods are available to set up transactors for specific tests, some of the more popular methods are introduced here.

File Read Method

This method is very common, especially in commercially available testbenches.

The transactor reads commands from an input file and executes them, creating stimulus and verifying responses for the testbench. For each simulation the input files for the simulated test need to be copied into the working directory. Usually this method is combined with a pre-processor which generates the input files, as described in the perl section.

Some problems of this approach are:

• Usually the input file format does not support sophisticated structural elements (loops, procedures etc) and VHDL is not really suited to implement a sophisticated parser
• Syntactical errors in the input file are usually only found during simulation time (this may result in the loss of valuable computing time)
• Lack of feedback: it's usually not possible to react flexibly on the response of the DUT by examining the value of signals etc
• The input "language" is not standard VHDL and therefore not immediately understandable to other designers

Some of the benefits are:

• The testbench VHDL can remain clean and should run on all platforms without any changes
• The testbench structure is straightforward, no configuration statements are required